High-speed networks are continually evolving. The evolution includes continual advances in the operational speed of the networks. The network implementation of choice that has emerged is Ethernet networks physically connected over unshielded twisted pair wiring. Ethernet in its 10/100BASE-T form is one of the most prevalent high speed LANs (local area network) for providing connectivity between personal computers, workstations and servers.
High-speed LAN technologies include 100BASE-T (Fast Ethernet) and 1000BASE-T (Gigabit Ethernet). Fast Ethernet technology has provided a smooth evolution from 10 Megabits per second (Mbps) performance of 10BASE-T to the 100 Mbps performance of 100BASE-T. Gigabit Ethernet provides 1 Gigabit per second (Gbps) bandwidth with essentially the simplicity of Ethernet. There is a desire to increase operating performance of Ethernet to even greater data rates.
FIG. 1 shows a block diagram of a pair of Ethernet transceivers communicating over a bi-directional transmission channel, according to the prior art. An exemplar transmission channel includes four pairs of copper wire (links) 112, 114, 116, 118. The transceiver pair can be referred to as link partners, and includes a first Ethernet port 100 and a second Ethernet port 105. Both of the Ethernet ports 100, 105 include four transmitter TX, receiver RX, and I/O buffering sections corresponding to each of the pairs of copper wires 112, 114, 116, 118.
Successfully implementing high speed Ethernet networks supporting full-duplex transmission in a single frequency band is challenging. For long loop lengths, recovering the transmitted information requires significant computational resources. High-precision, high-speed signal-processing is required to be able to successfully decode the signal, often involving multiple filters that span many hundreds of taps.
Present Ethernet technology can include time domain processing of digital or analog signal streams to aid in detecting the received data and minimizing the harmful interference afflicting the received data. With the increasing data transmission rates, the electronic hardware required to implement the time domain processing increases dramatically.
Communication systems typically use filtering to reduce interference and distortion of Ethernet signals to help the receiver reliably decode the data transmitted by the remote link partner with a high probability. Applications where filtering can be used to improve data transport reliability include, for example, adjacent and co-channel interference rejection, transmit signal shaping, data equalization, echo cancelation near-end cross-talk cancellation, far end cross-talk cancelation, external noise or interference cancellation, non-linear interference cancellation, etc. A common filter implementation that can be utilized in many filtering functions is finite impulse response (FIR) filtering.
Time domain FIR filtering can potentially result in a costly hardware implementation. For example, if an FIR filter has a length P (taps), then in general, roughly P multiply and accumulate (MAC) operations are required per filtered output sample. Depending on the filter application, a large number of filter taps could be required to successfully achieve the filtering objective. The electronic circuitry required to implement such high performance FIR fitters can then become very large, resulting in increased chip complexity, area, and power dissipation. Ethernet transceivers may need to implement filters that require 50-1000 taps (P), in which each filter tap operates on a filter input signal sample that is delayed by one (or fraction of one) symbol period from filter input signal sample the next filter tap operates on. Additionally, high performance Ethernet systems can require multiple long filters to operate successfully.
For example, Ethernet systems can require echo, Near-end cross talk (NEXT) and Far-end cross talk (FEXT) cancellation and data equalization. Additionally, Ethernet systems generally include 4 adjacent twisted pair connections per communication link, requiring echo, NEXT and FEXT cancellation as well as data equalization for each of the pairs. Therefore, an Ethernet system would typically include four echo-cancellation filters, four data-equalization filters, twelve NEXT-cancellation filters and twelve FEXT-cancellation filters.
Block-processing or domain-transformation techniques can be used to implement filtering in a way that significantly reduces the hardware implementation costs for long filters. An example of such an implementation is one using fast-Fourier-transform processing to implement the filtering.
While block-processing results in significantly lower complexity, block processing usually introduces additional processing delay, or latency, because of the block-by-block processing, often involving buffering a block of filter input samples before transforming them to the efficient filtering domain. The latency of a signal processed through a transceiver is an important system parameter that is desirable to minimize. Having high-latency can result in too much delay affecting the transmission of data and can adversely affect network systems requiring low-latency transmission of data. For applications requiring low-latency processing, the block by block processing used to reduce the transceiver hardware complexity can compromise the processing latency.
It is desirable to have an apparatus and method for supporting both lower latency processing as well as hardware efficient higher latency processing, for processing signal streams for reducing interference of Ethernet LAN signals to aid in receiver data detection. The lower latency and higher latency processing should require a minimal amount of electronic hardware, and dissipate a minimal amount of power.